Release Notes v0.18.5

This release includes features that bring us closer to adopting our new compiler, Rio, which is currently in beta.


  • We have introduced a new compiler stage within LLVM that lets us optimise configuration for our FPGA target, as opposed to conventional software.
  • Loop unrolling has been turned off for any loop that contains a function. This feature is set to be reversed once we have made improvements to our loop-unrolling cost model, so we can avoid performance regressions due to duplicated functions using excessive FPGA resources. v0.18.3

This release includes bugfixes and new features which bring us closer to adopting our new compiler, Rio, which is currently in beta.


  • Moved over to use the new compiler, Rio, for a subset of our internal test suite.
  • Added operating clock frequency to the reports generated during the build and sim processes. Now, when viewing reports, you will see both FPGA resource usage stats and the operating frequency of the final design.
  • Made some fixes to our SDAccel package to ensure its functionality with our new compiler design. The package functionality remains unchanged but you will need to use the most recent version if you are trying out the beta compiler in your designs.


  • Fixed a bug that was leading to invalid Verilog being generated, causing circuits to lock up.
  • Fixed a bug in the new compiler, which was allowing excessively long Verilog identifier names to be generated, which weren’t supported. This length has been limited to comply with vendor tooling requirements. v0.18.1

In this release, register-based scheduling is introduced to allow more parallel behaviour, and we’ve enabled blockRAM generation for designs using the new compiler, rio.


  • Register-based scheduling has been introduced in the compiler, which increases parallel behaviour by allowing independent, non-combinatorial components to be scheduled in parallel.
  • BlockRAMs are now generated when designs feature arrays larger than 512 bits. v0.18.0

This release presents a beta version of our new reworked compiler based on the LLVM infrastructure. The new compiler delivers significant performance and usablity improvements: around 30% lower latency, 30% lower utilization and closer alignment between our modelling and the Go language. To use the beta version of Rio for your projects have a look at the guidance here. v0.17.6

This is a bugfix release focussed on enabling some in-house product tests.


  • If a vendored version of our xcl library is provided, this is now given priority over our host-side code.
  • The default xcl library has been updated to include fixes for a segfault and to allow memory proceed to run while a kernel is running. v0.17.5

This is a bugfix release focussed on fixing unintended side-effects of some recent compiler optimizations.

  • Fixed an edge case in our latch scheduling algorithm where many serial forks would not introduce a latch, causing timing to fail. Thanks to foolmarks on our forums for reporting the bug!
  • Refined an optimization rule to prevent it from removing necessary control flow. v0.17.4

This release delivers significant performance improvements through simplifying logic and the way we handle constants. The result is faster and smaller arithmetic and logic operations, improved latch removal, and the ability to have multiple operators per clock cycle.

  • Simplified adjacent constants – two constants that are joined together will now be a single constant.
  • Changes to priorities for latch removal in order to remove more.
  • An entirely new cost system for latch removal based upon FPGA timing delay, along with reworked operators that allow them to complete in partial cycles, allowing simple arithmetic like (a + 1) < b to happen in a single cycle. v0.17.3

This is a performance focused release that includes some bugfixes related to larger applications

  • Reworked multipliers to use fewer pipeline stages, improving performance
  • Optimize control flow around some channel operations
  • Optimize expressions like n < 0 to just check the sign bit.
  • Fix an issue with some module names being too long for Vivado
  • Fix an issue where reco.yml files using Windows line ending were not being parsed correctly v0.17.2

This is a bugfix release focussed on graph generation.

  • Fixed a bug in our optimization rules which lead to some graphs being incorrectly generated. v0.17.1

This release adds support for increased memory access bandwidth, from 64 bit to 512 bit, when using the new SMI infrastructure. This will provide a performance gain when using read/write burst memory transactions. See an example application using SMI here.

A draft version of our SMI API docs is now available.

  • You can now set memory read/write bandwidth to 512 bit. v0.17.0

This release adds initial support for our new memory infrastructure, called SMI (Scalable Multiprotocol Infrastructure).

Our engineers have developed SMI to provide improvements to the way we give memory access to FPGAs. Improvements through using SMI include:

  • Easier to scale up projects to use available memory bandwidth.
  • Increase in available bandwidth across multiple goroutines.
  • Simplified code, less boilerplate.
  • Further optimize some variable and channel concurrency operations.
  • Reduce verbose log output during synthesis. v0.16.4

This is a minor release focused on improving performance for generated code, and fixing a bug in our sdaccel support.

  • Reduce the cost of functions calls.
  • Optimize some variable and channel concurrency operations.
  • Fix an issue in code generation where the ReadBurst memory functions could lock up when the consumer was too slow. v0.16.3

This is a bugfix release fixing generated code causing a crash in some vendor tooling.

  • Altered the representation of BRAM initilization constants to prevent segfaults during synthesis. v0.16.2

This is a bugfix release targeting bugs in consecutive channel reads and graph generation.

  • Optimized code generation in the case of consecutive channel reads, reducing the size of the resulting circuit on the FPGA.
  • Fixed a bug which caused graph generation to crash.
  • Fixed a bug in code generation where consecutive channel reads would result in code that would not build on FPGAs. v0.16.0

In this release, we have open sourced our Go libraries that were previously included as part of the build process. This allows for better integration with local tooling.

This upgrade is purely an opt-in process. The previous packages will continue to work.

If you’d like to upgrade, we provide a tool to automigrate your code. Run it like so:

$ go install
# In your project directory
$ fix .

You’ll also need to use Go’s vendor mechanism to vendor the version of our tools you’d like to use. We recommend using Glide to manage the vendor folder:

$ glide create --non-interactive
$ glide install
$ ls vendor/
axi  cmd  control  LICENSE  Makefile  stubs  verilog  xcl  framework.go  docker-compose.yml
  • Our compiler now supports multiple function arguments with the same type, of the form: func myFunction(a, b, c int)
  • The compiler now correctly typechecks arguments to functions.

    Previously, some types with equal representation would be allowed (e.g. uint and uint32) interchangably as arguments to a function call. This fixes that, and improves error messages in the cases that were already covered. v0.15.0

This release marks our public beta! We’re tremendously excited to put the product out into the world. In addition, this release contains performance tweaks that will improve the speed of much real-world code.

  • The compiler now supports an optimization known as operator pipelining. Whenever the compiler encounters a loop that processes data arithmetically, it converts that loop into a highly-efficient pipeline on the FPGA, during which one piece of data may allow a subsequent piece of data to start before the current datum has finished processing. Parallel stages are balanced through latch insertion. This provides drastic speedups to any program that features looped processing of data.
  • We have adjusted the optimization rules to take advantage of highly-pipelined programs.
  • Bugs in on-chip SELF components have been fixed.
  • Potential inefficiencies when mixing constants and variables in arithmetic operators have been removed. v0.14.0

This release delivers performance improvements.

  • The compiler can now inline idempotent constant functions, which can lead to significant performance improvements.
  • A new optimization algorithm has been applied, which can rewrite arithmetic expressions into more-performant equivalents.
  • Bugs in the implementation of low-level SELF components have been fixed.
  • Latches that break loops have been made more correct. v0.13.0

This release delivers major performance improvements.

  • Added ability to specify constant capacities to channels, e.g. c := make(chan uint, 3) provides a channel of capacity 3.
  • Latch reduction was overhauled, resulting in more efficient networks. Kernels are typically 30% - 50% faster than they were before.
  • Kernels are now reset before running, fixing issues with some kernels locking up after multiple runs.
  • Multiple variables may be declared in one var declaration, as per the Go spec. v0.12.8

This is a minor performance release.

  • Improved performance of channels, saving 3 cycles for a send/receive pair.
  • Improved performance by combining variable writes where possible. v0.12.7

This is a bugfix release that unblocks the release of our fixed point library.

  • Fixed a bug where casting to a type in another package would cause an error
  • Fixed a bug where vendor packages weren’t being considered in host side code
  • Fixed a bug where dependencies of dependencies would cause an error
  • Internal rework of our channel implementation, which should give us a better foundation in the future. You may notice slight performance regression because of this, until we make sure it has performance parity with the previous implementation. v0.12.6

This is a bugfix release to handle an issue specific to Windows.

  • Fixed a bug where directories from input artifacts were not treated as directories. This could manifest in unfound executables. v0.12.5

This is a minor release to officially support external libraries in our build process.

  • Kernels can now include a vendor directory, much like Go’s vendor support.
  • reco is now versioned, with the release of v0.2.0. If you have previously downloaded reco, run the new commands in Getting Started – Let’s Deploy Some Code!.
  • reco check will now auto update. v0.12.4

This is a minor release to improve some error messages.

  • Improved error messages when using an identifier incorrectly v0.12.3

This is a bugfix release, focused on fixing bugs & performance issues found in larger programs.

  • Automatic pruning of unused code. Synthesis of generated code is now faster, and compilation to Verilog is 10x faster.
  • Improved error messages when trying to use a struct as a function.
  • Compiler now checks to ensure that a function has a return statement.
  • Fixed scoping bug in reco check.
  • Fixed bug where identifiers that did not begin with an uppercase letter were exported.
  • Improved the error message when attempting to shift by a negative number v0.12.1

This is a bugfix release, focused on fixing issues identified by larger example programs.

  • Algorithm optimizations in our optimization engine, decreasing compile times for larger programs by a significant amount. This will be most noticeable on simulations, where compile times take a significant amount of the total runtime.
  • Performance improvements in our AXI arbitration library.
  • Fixed an issue coercing literals to type aliases.
  • Fixed an issue with uninitialized variables causing a compiler error.
  • Fixed an issue where high fanout wires could be generated in output Verilog. v0.12.0

  • Added the ability to generate and view PDFs of the intermediate graphs. See reco graph and it’s accompanying documentation.
  • Reworked the reco command line tool to break out subcommands
  • Fixed certain arithmetic expressions that were treated as ill-typed due to improper constant propagation v0.11.0

  • Constant expressions in array lengths are now supported.
  • Improved performance of optimization rules.
  • Improved overall performance by preventing RAM generation for insufficiently-large arrays.
  • Reduced compile times by tweaking the optimization engine.
  • A 15 minute time limit has been added to simulation times.
  • A 12 hour time limit has been added to build times.
  • Fixed inconsistent RAM instantiation, which was resulting in breaking code.
  • Fixed reco-check - no longer giving an error on float32 & float64. v0.10.0

We’re excited to announce that deployments to F1 instances are now operational!

  • Deployments, created through the reco run command, are now enabled on all accounts. v0.9.1

This release is focused on performance improvements in the compiler.

  • Heuristics were added to the compiler to combine arithmetic & logical operators, improving area & speed. For more details, see our post about it.
  • The reco check command now respects projects, like the other commands. v0.9.0

This release is focused on providing a quick way to check your code is compatible with our compiler.

  • Inclusion of the command reco check, allowing for users to type check kernel code locally.
  • Fixed Windows bugs for reco.
  • Optimization rules for small arrays have been adjusted, fixing long build times.
  • Error messages upon encountering unsupported defer-statements have been improved. v0.8.0

This release is focused on enabling RAMs & documentation of the API.

  • Add publishing of godoc to the build process.
  • Support RAM blocks for arrays of sufficient size, providing significant performance improvements.
  • Arrays larger than 2^31 - 1 are now formally rejected by the compiler.
  • A bug associated with side-effects in binary assignment operators has been fixed.
  • Use of unsupported multiple-assignment is now flagged rather than failing silently.
  • The behavior of the _ wildcard now complies more closely with the mainline Go compiler.
  • Issues with generating invalid Verilog variable names have been fixed. v0.6.0

This release is focused on optimizations and bugfixes in the compiler.

  • Enable intermediate variable analysis & optimizations.

More code should be able to run without synthesis errors, and code that relied on intermediate variables should see a significant increase in performance.

  • Anonymous structs are now supported.
  • Octal literals are now supported.
  • Position information has been attached to more error messages.
  • Bugs in parsing certain hexadecimal literals have been fixed.
  • For-loops that omitted a final statement would be rejected. This has been fixed. v0.5.0

This release is focused on speed and reliability of the build process, and introduces our new reco tool.

  • reco is now the preferred tool. Workflows using reco-jarvice will still work, but are deprecated.
  • Fix a hardware configuration that allowed The placer database file is corrupted. Expected (section_tag_sitecontent): 0xdead3333 found: 0 to happen under load. v0.4.0

This release is focused on expanding concurrency primitives, and providing better error messages.

  • Multiple go routines can now write to a channel.
  • Error messages are now easier to understand, colourized, tagged and location-aware.
  • Simplification of output verilog. v0.3.0

This release is focused on adding concurrency primitives to the compiler.

  • Added preliminary support for select statements.

select statements of the following form are supported.

select {
  case a <- chan1:
  case b <- chan2:

Several restrictions apply:

  • It is not possible to output to a channel in a select statement.
  • Input channels must be static identifiers.
  • Using multiple select statements with the same channel will result in an error.
  • Added MemoryReader & MemoryWriter with corresponding io.Reader and io.Writer instances to the xcl library.
  • Fixed some issues with variable sythesis causing crashes.
  • Fixed possible segfaults in xcl. v0.2.1

This release is focused on improving the compiler, and improving the reliability of the build process.

  • We have made the build process more resilient to network issues, which means fewer failures.
  • Multiplication & division have been enabled. All of Go’s arithmetic & logical operators are now supported.
  • Compiler error messages will now include line & column information.
  • Fixed an issue with assignment to struct members.
  • Fixed an issue with side-effecting returns in for loops.
  • An error message is thrown if the user attempts to assign to a channel more than once. v0.1.0

This is the first alpha release of our tooling, allowing the development and deployment of kernels written in Go to FGPAs using the SDAccel framework.

  • Initial support for translating a single Go file.
  • Libraries to support 32 bit access to on-card memory.
  • Support for simulating & building FGPA accelerated applications, through the reco-jarvice command line tool.

The tooling and compiler are in an alpha state. Though our offering is polished enough to get real-world tasks done, there are as of yet some rough edges and incompatibilities. These will all be addressed in subsequent releases, and we appreciate your patience in the meantime.

A core part of the language is supported, including functions, methods, and primitive operators. The following limitations apply in this release:

You may be able to work around this limitation through bitshifts and repeated addition.

Depending on the underlying type, arrays of more than length 64 may result in code that cannot be run on an FPGA. To work around this, use the memory interface.

You can’t use a function that’s declared later than it’s used in your code. To work around this, only use a function or method after it’s declared.

Most libraries will not work on FPGAs. If this interferes with your vision, please let us know which libraries you’d like to see supported by the tooling and compiler.

The alpha release does not support IEEE-754 floating point operations, as expressing IEEE-754 on an FPGA is a nontrivial problem. This will be addressed in future releases!

You may be able to work around the lack of maps with judicious use of arrays.

Channels must be statically resolvable at compile time. In this case, you may bind a channel to a name only once. The following code will error:

func badChannelUsage(){
     c := make(chan int)
     b = c

Pointers & slices are not supported. Some slice usage can be replaced by arrays.

Build, simulations & running jobs are limited to a 2 hour timeout.

Tooling only supports ‘Jarvice’ provider. In future reco-jarvice will be replaced with reco which will support multiple cloud providers.